Footprint Design Optimization in SiGe BiCMOS SOI Technology

被引：14

作者：

Chen, Tianbing ^{[1
]}

Babcock, Jeff ^{[1
]}

Nguyen, Yen ^{[1
]}

Greig, Wendy ^{[1
]}

Lavrovskaya, Natasha ^{[1
]}

Thibeault, Todd ^{[1
]}

Ruby, Scott ^{[1
]}

Adler, Steve ^{[1
]}

Krakowski, Tracey ^{[1
]}

Kim, Jonggook ^{[1
]}

Sadovnikov, Alexei ^{[1
]}

机构：

[1] Natl Semicond Corp, Adv Proc Technol Dev, Santa Clara, CA 95052 USA

来源：

PROCEEDINGS OF THE 2008 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING | 2008年

关键词：

SiGe HBT; footprint; safe operating area; self heating; thermal resistance; impact ionization;

D O I：

10.1109/BIPOL.2008.4662745

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Footprint design in SiGe BiCMOS SOI technology is described in this paper to improve device performance matrix. The safe operating area (SOA) for a SiGe hetero-junction bipolar transistor (HBT) fabricated on silicon on insulator (SOI) is significantly improved as the footprint area increases. The Early voltage for SiGe HBT on SOI at medium-high bias range also increases substantially with footprint area increase. Peak f(T) and noise figure improves slightly with footprint, and peak f(MAX) improves slightly then decreases significantly at very large footprint area. A generic tube-area-limited thermal resistance model for BiCMOS devices on SOI is also proposed.

引用

页码：208 / 211

页数：4

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