An augmented chained fault-tolerant ATM switch

被引：1
|
作者：
Hui, SK [1 ]
Seman, K [1 ]
Yunus, J [1 ]
机构：
[1] Univ Teknol Malaysia, Fac Elect Engn, Skudai 81300, Johor, Malaysia
来源：
HSNMC 2002: 5TH IEEE INTERNATIONAL CONFERENCE ON HIGH SPEED NETWORKS AND MULTIMEDIA COMMUNICATIONS | 2002年
关键词：
D O I：
10.1109/HSNMC.2002.1032616
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
A new fault-tolerant ATM switch architecture based on Multistage Interconnection Network (MIN) was proposed. Multiple paths between each input-output pair of the network are accomplished by connecting together switching elements within the same stage. Besides that, 2(n)2x2 switching element were distributed between stage n to n+1 in MIN to increase the paths for each input-output pair. It is self-routing, recursive in structure and smaller network easily be cascaded to form larger network. Compared to the conventional mechanism, it reduces delay and gives better performance in term of stability and throughput
引用
收藏
页码：397 / 400
页数：4
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