Rapid development of structured simulation models for the verification of discrete-event control systems

This paper demonstrates the use of state-of-the-art controller synthesis and modelling/simulation paradigms for building and testing "verifiable" discrete-event control systems. The proposed approach reduces the occurrence of errors during the generation of the control system model, thus speeding the specification-synthesis-verification cycle and diminishing substantially implementation tasks. The approach is illustrated with an example of industrial complexity and size. Copyright (C) 1998 IFAC.