Single-phase hybrid cascaded H-bridge and diode-clamped multilevel inverter with capacitor voltage balancing

被引:26
作者
Castillo, Richard [1 ]
Diong, Bill [1 ]
Biggers, Preston [1 ]
机构
[1] Kennesaw State Univ, Dept Elect Engn, 1100 S Marietta Pkwy, Marietta, GA 30060 USA
关键词
IMPLEMENTATION; TOPOLOGIES; CONVERTER; PWM;
D O I
10.1049/iet-pel.2017.0009
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Diode-clamped and cascaded H-bridge multilevel inverters are two of the main multilevel inverter topologies; each has its distinct advantages and drawbacks. Regarding the latter, cascaded H-bridge inverters require multiple separate dc sources, whereas (semi-active) diode-clamped inverters contain capacitors that require a means to balance their voltages. This paper investigates a hybrid-topology inverter, comprising a single-phase five-level semi-active diode-clamped inverter and a single-phase cascaded H-bridge inverter with their outputs connected in series, as one way to mitigate the drawbacks of each topology. The proposed control scheme for this inverter operates the switches at fundamental frequency to achieve capacitor voltage-balancing while keeping the switching losses low. Moreover, the step-angles are designed for the 13-level and 11-level output voltage waveform cases (as examples) for a fixed modulation index to achieve optimal total harmonic distortion. Furthermore, the scheme also achieves capacitor voltage-balancing for modulation indices that are close to the optimal modulation index, and for a wide range of load power factors, albeit at the cost of increased output voltage distortion. Simulation results are presented to help explain the processes of capacitor recharging and voltage-balancing, while experimental results are shown as verification of the expected behaviour of this inverter and the proposed control scheme.
引用
收藏
页码:700 / 707
页数:8
相关论文
共 25 条
[1]  
[Anonymous], 5192014 IEEE
[2]  
[Anonymous], EUR POWER ELECT DRIV
[3]  
Baker I.R.H., 1975, U.S. Patent, Patent No. [3,867,643, 3867643]
[4]  
Chaulagain M., 2016, IEEE SOUTHEASTCON, P1
[5]   Research on hybrid-clamped multilevel-inverter topologies [J].
Chen, Alian ;
He, Xiangning .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2006, 53 (06) :1898-1907
[6]  
Diong B, 2012, IEEE ENER CONV, P1540, DOI 10.1109/ECCE.2012.6342630
[7]   Harmonic Distortion Optimization of Cascaded H-Bridge Inverters Considering Device Voltage Drops and Noninteger DC Voltage Ratios [J].
Diong, Bill ;
Sepahvand, Hossein ;
Corzine, Keith A. .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2013, 60 (08) :3106-3114
[8]   Fundamental Frequency Switching Strategies of a Seven-Level Hybrid Cascaded H-Bridge Multilevel Inverter [J].
Du, Zhong ;
Tolbert, Leon M. ;
Ozpineci, Burak ;
Chiasson, John N. .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2009, 24 (1-2) :25-33
[9]  
Fang Zheng Peng, 1994, Power Quality '94 USA. Official Proceedings of the Seventh International Power Quality Telecomputer Infrastructure Conference (Power Quality), P58
[10]  
Hayden C. L., 1979, INTELEC 79. International Telecommunications Energy Conference, P316