Design of phase-locked loops for digital signal processors

被引：0
|
作者：
Leonov, Gennadii [1 ]
Seledzhi, Svetlana [1 ]
机构：
[1] St Petersburg State Univ, Fac Math & Mech, St Petersburg, Russia
来源：
INTERNATIONAL JOURNAL OF INNOVATIVE COMPUTING INFORMATION AND CONTROL | 2005年 / 1卷 / 04期
关键词：
stability; phase-locked loop; processor; clock skew;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Digital signal processors (DSP) are widespread in real-time systems. In the last ten years phase-locked loops have widely been used in DSP as control devices correcting a clock skew. In this paper new type of floating phase locked loops for DSP is designed. For the floating phase locked loops new stability conditions are obtained.
引用
收藏
页码：779 / 789
页数：11
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