The Multi-input MRL Logic Gate and Its Application

被引：2
|
作者：
Qu, Li [1 ]
Cui, Xiaole [1 ]
Xu, Xiaoyan [1 ]
Cu, Xiaoxin [2 ]
Ma, Ye [1 ]
机构：
[1] Peking Univ, Key Lab Integrated Microsyst, Shenzhen Grad Sch, Shenzhen, Peoples R China
[2] Peking Univ, Inst Microelect, Beijing, Peoples R China
来源：
2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2019年
关键词：
memristor; MRL; multi-input MRL gates;
D O I：
10.1109/edssc.2019.8753985
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper discusses the design constraints on the multi-input Memristor Ratioed Logic (MRL) AND and OR gates, and it is found out that the number of inputs is limited by the resistance ratio between the high resistance and low resistance values. A design case of a 4-1 multiplexer with the multi-input MRL gates is presented. The simulation results show that it has a smaller area and higher speed compared with that of the counterpart with the two-input MRL gates.
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页数：2
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