Analysis and Design of an Overcurrent Protection Scheme Based on Parasitic Inductance of SiC MOSFET Power Module

被引：0

作者：

Sun, Keyao ^{[1
]}

Wang, Jun ^{[1
]}

Burgos, Rolando ^{[1
]}

Boroyevich, Dushan ^{[1
]}

Kang, Yonghan ^{[2
]}

Choi, Edward ^{[2
]}

机构：

[1] Virginia Polytech Inst & State Univ, Ctr Power Elect Syst, Blacksburg, VA 24061 USA

[2] LG Elect USA Inc, 1835 Technol Dr, Troy, MI USA

来源：

THIRTY-THIRD ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC 2018) | 2018年

关键词：

SiC MOSFET Module; Gate Driver; Overcurrent Protection; Parasitic Inductance;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an overcurrent protection scheme based on parasitic inductance between the power source and the Kelvin source of the power module. A complete design process and comprehensive analysis of the overcurrent protection scheme, which can be applied generally, to any power module containing Kelvin source is shown. The protection circuit can be used to detect both very intense short-circuit fault (SC) and relatively slow overcurrent fault (OC), fault out of load for example. A 1.2 kV SiC MOSFET gate driver prototype with integrated overcurrent protection circuit is designed to verify the functionality of the protection method.

引用

页码：2806 / 2812

页数：7

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