An FPGA implementation of a GF(p) ALU for encryption processors

Secure electronic and internet transactions require public key cryptosystems to establish and distribute shared secret information for use in the bulk encryption of data. For security reasons, key sizes are in the region of hundred's of bits. This makes cryptographic procedures slow in software. Hardware accelerators can perform the computationally intensive operations far quicker. Field-Programmable Gate Arrays are well-suited for this application due to their reconfigurability and versatility. Elliptic Curve Cryptosystems over GF(p) have received very little attention to date due to the seemingly more attractive finite field GF(2 However, we present a GF(p) Arithmetic Logic Unit which can perform 160-bit arithmetic at clock speeds of up to 50 MHz. (C) 2004 Elsevier B.V. All rights reserved.