A low specific on-resistance SOI LDMOS with a novel junction field plate

A low specific on-resistance SOI LDMOS with a novel junction field plate (JFP) is proposed and investigated theoretically. The most significant feature of the JFP LDMOS is a PP-N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buried oxide layer (BOX) and thus widens the vertical conduction area. As a result, the breakdown voltage (BV) is improved and the specific on-resistance (R-on,R-sp) is decreased significantly. It is demonstrated that the BV of 306 V and the R-on,R-sp of 7.43 m Omega.cm(2) are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the R-on,R-sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and R-on,R-sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices.