NOVEL ARCHITECTURES OF MODULO 2n ± 1 ADDERS FOR FIELD PROGRAMMABLE GATE ARRAY

被引：0

作者：

Younes, Dina ^{[1
]}

Steffan, Pavel ^{[1
]}

机构：

[1] Brno Univ Technol, Microelect Dept, Tech 3058 10, Brno 61600, Czech Republic

来源：

ELECTRONIC DEVICES AND SYSTEMS: IMAPS CS INTERNATIONAL CONFERENCE 2011 | 2011年

关键词：

Residue Number System; modulo 2(n)+/- 1 adders; FPGA; prefix carry computation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents two new architectures of residue number system adders for moduli 2(n)-1, 2(n)+1. These two architectures allow efficient implementation on Field Programmable Gate Array (FPGA). Both designs depend on prefix carry computation, in order to speed up the computation time and get rid of the necessity to a second adder; the commonly used structure. Carry ripple adders (CRA) were used in this paper due to the dedicated carry ripple logic built-in FPGAs. The proposed designs were implemented on Spartan -3 xc3s200-ft256-4 FPGA. A comparison with published designs was done in terms of time and area consumption and showed time savings up to 44.7 %.

引用

页码：51 / 56

页数：6

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