A Hardware Implementation Method of the Aihara Chaotic Neural Network

被引：0
|
作者：
Xu, Guizhi [1 ]
Yang, Zhao [1 ]
Luo, Jie [1 ]
机构：
[1] Hebei Univ Technol, Key Lab Electromagnet Field & Elect Apparat Relia, Tianjin, Peoples R China
来源：
2016 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC) | 2016年
关键词：
chaotic neural network; pipeline; chaos characteristics; FPGA;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper briefly introduces the Aihara chaotic neural network, and then deduces and simplifies its original dynamics equation. Based on the idea of pipeline model, we established an Aihara chaotic neural network of four nervous. By the way of Altera Dsp Builder generating code, we made the simulation and hardware implementation on FPGA platform. Finally, we analyzed the output of the network and proved its good chaos characteristics.
引用
收藏
页码：1118 / 1121
页数：4
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