Efficient Distributed Memory Management in a Multi-Core H.264 Decoder on FPGA

被引：0

作者：

Zhang, Jiajie ^{[1
]}

Yu, Zheng ^{[1
]}

Yu, Zhiyi ^{[1
]}

Zhang, Kexin ^{[3
]}

Lu, Zhonghai ^{[2
]}

Jantsch, Axel ^{[2
,3
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China

[2] KTH Royal Inst Technol, Kista, Sweden

[3] Memcom Soc Microelect Co Ltd, Wuxi, Peoples R China

来源：

INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP (SOC) | 2013年

关键词：

Multi-core; DSM; H.264; decoder; DME; FPGA;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Memory management is a challenging issue of multi-core architecture. With growing core numbers, Distributed Shared Memory (DSM) is becoming a general trend. In this paper, a DSM based multi-core architecture is explored and evaluated via an H. 264 decoder application. The memory access and communication over Network-on-Chips is managed by the Data Management Engine (DME). Experimental results realized on an Altera Strati x VI show that 9-node distributed memory system increases performance by 1.5x compared to centralized memory. Moreover, the performance of proposed DSM architecture grows linearly with the number of cores deployed.

引用

页数：4

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