Some Notes about the History of Low-Power

his paper describes some events in the long history of Low-Power applied to integrated circuits. Four big steps are mentioned: 1) planar technology; 2) introduction of CMOS logic; 3) new advanced technologies with Vdd reduction; 4) introduction of numerous low-power design techniques. Unfortunately, after this "happy scaling", period, in the last decade, leakage and technology variations were severe new problems that have to be solved by many design techniques. The last question is the future of microelectronics, taking into account the end of Moore's law, the predictions of ITRS roadmap and the possible replacement of MOS transistors. Personal statement is that we see a very long life to CMOS, even if it is stuck at 28 to 16 nm. Being stuck at a given technology node, no performances improvement will be available at hardware level, contrary to the embedded software and system levels where a lot of work has to be performed for reducing power.