A 100-dB SFDR 80-MSPS 14-bit 0.35-μm BiCMOS pipeline ADC

被引：25
作者：
Bardsley, Scott [1 ]
Dillon, Christopher [1 ]
Kummaraguntla, Ravi [1 ]
Lane, Charles [1 ]
Ali, Ahmed M. A. [1 ]
Rigsbee, Baeton [1 ]
Combs, Darren [1 ]
机构：
[1] Analog Devices Inc, Greensboro, NC 27409 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2006年 / 41卷 / 09期
关键词：
analog-to-digital converter (ADC); boost; bootstrap; capacitor shuffling; comparator; flash; high speed; input buffer; latching comparator; pipeline; switched capacitor; CMOS ADC; CONVERTER;
D O I：
10.1109/JSSC.2006.880590
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes a 14-bit 80-MSPS ADC with 100-dB SFDR at 70-MHz input frequency in a 0.35-mu m single-well BiCMOS technology drawing 1.2 W from a dual 3.3 V/5.0 V supply. Key barriers to high dynamic range in pipeline ADCs at high clock rates and some methods to overcome these barriers will be presented. These methods include a sampling front-end without the use of a designated Sample and Hold (S/H). A BiCMOS switching input buffer is used along with the strategic use of BiCMOS design techniques. Also, calibration is combined with capacitor shuffling to maximize linearity with minimal noise impact.
引用
收藏
页码：2144 / 2153
页数：10
相关论文
共 10 条
[1]   A 14-b 20-MSamples/s CMOS pipelined ADC [J].
Chen, HS ;
Song, BS ;
Bacrania, K .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (06) :997-1001
[2]   A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR [J].
Chiu, Y ;
Gray, PR ;
Nikolic, B .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (12) :2139-2151
[3]   Inherently linear capacitor error-averaging techniques for pipelined A/D conversion [J].
Chiu, Y .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2000, 47 (03) :229-232
[4]   A power optimized 13-b Msamples/s pipelined analog-to-digital converter in 1.2 mu m CMOS [J].
Cline, DW ;
Gray, PR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (03) :294-303
[5]   A 15-B 1-MSAMPLE/S DIGITALLY SELF-CALIBRATED PIPELINE ADC [J].
KARANICOLAS, AN ;
LEE, HS ;
BACRANIA, KL .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (12) :1207-1215
[6]   A 13-B 2.5-MHZ SELF-CALIBRATED PIPELINED A/D CONVERTER IN 3-MU-M CMOS [J].
LIN, YM ;
KIM, B ;
GRAY, PR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (04) :628-636
[7]   A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC [J].
Mehr, I ;
Singer, L .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (03) :318-325
[8]   A 14-bit 100-msample/s subranging ADC [J].
Moreland, C ;
Murden, F ;
Elliott, M ;
Young, J ;
Hensley, M ;
Stop, R .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (12) :1791-1798
[9]  
OCKEY R, 1999, P IEEE CAN C EL COMP, V1, P403
[10]   A 3-V 340-mW 14-b 75-msample/s CMOS ADC with 85-dB SFDR at Nyquist input [J].
Yang, WH ;
Kelly, D ;
Mehr, I ;
Sayuk, MT ;
Singer, L .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (12) :1931-1936
1