共 33 条
[1]
Azar K. Z., 2019, IACR Trans. Cryptogr. Hardw. Embed. Syst, P97, DOI DOI 10.46586/TCHES.V2019.I1.97-122
[2]
Preventing IC Piracy Using Reconfigurable Logic Barriers
[J].
IEEE DESIGN & TEST OF COMPUTERS,
2010, 27 (01)
:66-75
[3]
Chakraborty R, 2018, 2018 2ND INTERNATIONAL CONFERENCE ON ELECTRONICS, MATERIALS ENGINEERING & NANO-TECHNOLOGY (IEMENTECH), P6
[4]
Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks
[J].
PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC),
2019,
[5]
LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection
[J].
2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI),
2018,
:405-410
[7]
The Model with Left Bottom Corner Coordinates for 2D Rectangular Strip Packing Problem
[J].
PROCEEDINGS OF THE 2017 INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND APPLICATIONS (WCNA2017),
2017,
:172-176
[9]
Rajendran J, 2012, DES AUT CON, P83
[10]
SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware
[J].
PROCEEDINGS OF THE 2018 GREAT LAKES SYMPOSIUM ON VLSI (GLSVLSI'18),
2018,
:153-158