Hardware/software codesign of a scalable embedded radar signal processor

被引：5

作者：

Buenzli, C

Owen, L

Rose, F

机构：

来源：

VHDL INTERNATIONAL USERS' FORUM, PROCEEDINGS | 1997年

关键词：

D O I：

10.1109/VIUF.1997.623951

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The RASSP performance modeling methodology was used to rapidly model and compare alternative hardware/software architectures for a scalable embedded radar signal processor based on COTS DSP boards. VHDL performance models were generated from graphical hardware and software architectures using Cosmos(TM), simulated with QuickHDL(TM), and analyzed with Cosmos. Results for a Mercury RACEway(TM) architecture are presented.

引用

页码：200 / 208

页数：3