Securing FPGA-Based Obsolete Component Replacement for Legacy Systems

被引:0
作者
Zhang, Zhiming [1 ]
Njilla, Laurent [2 ]
Kamhoua, Charles [3 ]
Kwiat, Kevin [2 ]
Yu, Qiaoyan [1 ]
机构
[1] Univ New Hampshire, Dept Elect & Comp Engn, Durham, NH 03824 USA
[2] Air Force Res Lab, Cyber Assurance Branch, Rome, NY 13441 USA
[3] Army Res Lab, Adelphi, MD 20783 USA
来源
2018 19TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED) | 2018年
关键词
FPGA security; FPGA Trojan; Hardware security; hardware Trojan; legacy system; obsolete component replacement; pin grounding;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Component-aging is unavoidable in legacy systems. Although re-designing the system typically results in a high cost, the need to replace aged components for legacy systems is an urgent priority. Unfortunately, the aged components are likely to be obsolete and not available on the current market. Obsolete component replacement with field-programmable gate array (FPGA) devices is emerging as a feasible option to extend the lifetime of legacy systems. While replacing the aged component, we traditionally only focus on matching the functionality and neglect the potential security threats from FPGA replacement. However, recent literature demonstrates that FPGA devices may contain hardware Trojans, which are induced during FPGA device fabrication or bitstream generation time. To prevent the Trojans on FPGA from receiving external inputs or leaking sensitive information, we propose a Runtime Pin Grounding (RPG) scheme to ground the unused pins and check the pin status at every clock cycle. Furthermore, we exploit the principle of moving target defense (MTD) and propose a hardware MTD (HMTD) method. In our method, the aged obsolete unit is replicated to multiple copies in the FPGA device, and two of the replicas are randomly selected for output comparison and thus Trojan detection. We successfully implemented the proposed RPG and HMTD methods on a Nexys-3 FPGA board. Our case study shows that the proposed RPG scheme increases the FPGA utilization rate by less than 0.1%. On average, our HMTD method reduces the hardware Trojan bypass rate by 61% over the existing method.
引用
收藏
页码:401 / 406
页数:6
相关论文
共 15 条
[1]  
Bloom G, 2015, 2015 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST (HOST), P48, DOI 10.1109/HST.2015.7140235
[2]   Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream [J].
Chakraborty, Rajat Subhra ;
Saha, Indrasish ;
Palchaudhuri, Ayan ;
Naik, Gowtham Kumar .
IEEE DESIGN & TEST, 2013, 30 (02) :45-54
[3]  
Drimer S., 2008, Volatile FPGA Design Security-A Survey
[4]  
Hadzic I., 1999, Field Programmable Logic and Applications. 9th International Workshop, FPL'99. Proceedings (Lecture Notes in Computer Science Vol.1673), P291
[5]  
Hallmans D, 2015, IEEE INTL CONF IND I, P208, DOI 10.1109/INDIN.2015.7281736
[6]  
Jyothi V, 2016, PR IEEE COMP DESIGN, P600, DOI 10.1109/ICCD.2016.7753346
[7]  
Karam R., 2016, 2016 INT C RECONFIGU, P1, DOI DOI 10.1109/SCEECS.2016.7509283
[8]  
Karam R, 2017, ASIA S PACIF DES AUT, P611, DOI 10.1109/ASPDAC.2017.7858391
[9]   Design and Validation for FPGA Trust under Hardware Trojan Attacks [J].
Mal-Sarkar, Sanchita ;
Karam, Robert ;
Narasimhan, Seetharam ;
Ghosh, Anandaroop ;
Krishna, Aswin ;
Bhunia, Swarup .
IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS, 2016, 2 (03) :186-198
[10]   Hardware Trojan Attacks in FPGA Devices: Threat Analysis and Effective Countermeasures [J].
Mal-Sarkar, Sanchita ;
Krishna, Aswin ;
Ghosh, Anandaroop ;
Bhunia, Swarup .
GLSVLSI'14: PROCEEDINGS OF THE 2014 GREAT LAKES SYMPOSIUM ON VLSI, 2014, :287-292