Compact and Compound SCR structure for full chip ESD protection

被引：12

作者：

Dong, Xiaoyu ^{[1
]}

Du, Feibo ^{[1
]}

Hou, Fei ^{[1
]}

Song, Wenqiang ^{[1
]}

Liu, Zhiwei ^{[1
]}

Liu, Jizhi ^{[1
]}

机构：

[1] Univ Elect Sci & Technol China, State Key Lab Elect Thin Films & Integrate Device, Chengdu, Sichuan, Peoples R China

来源：

2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2019年

关键词：

CMOS; SCR; full chip ESD protection; area consumption; DESIGN;

D O I：

10.1109/edssc.2019.8754315

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Traditional full chip electrostatic discharge (ESD) protection circuits consumes a large amount of chip area. To resolve this problem, a novel three-terminal compact and compound SCR (CCSCR) is proposed. The proposed CCSCR employs intrinsic parasitic SCRs and ESD diodes as main ESD discharge paths to independently implement full chip ESD protection, which can greatly reduce area consumption and achieve high ESD robustness. The TCAD simulation indicates that the proposed CCSCR has a low trigger voltage and a high holding voltage. In addition, RC detection circuit is also introduced into CCSCR to further reduce the trigger voltage and improve the holding voltage, which makes CCSCR more efficient as a candidate ESD device in nanoscale CMOS technology.

引用

页数：2

共 5 条

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