Skipping Embedding in the Design of Reversible Circuits

被引:3
作者
Zulehner, Alwin [1 ]
Wille, Robert [1 ]
机构
[1] Johannes Kepler Univ Linz, Inst Integrated Circuits, Linz, Austria
来源
2017 IEEE 47TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2017) | 2017年
关键词
LOGIC; ALGORITHM; LINES;
D O I
10.1109/ISMVL.2017.19
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Synthesis of reversible circuits finds application in many promising domains but has to deal with the fact that the underlying circuits require a unique mapping from the inputs to the outputs. Existing solutions addressed this problem by additionally performing a so-called embedding process prior to synthesis or by naively mapping building blocks of conventional logic to their corresponding reversible counterparts. This leads to solutions that either suffer from limited scalability or yield circuits with a huge number of additionally required circuit lines. In this work, we conduct investigations to overcome these problems. To this end, we simply ignore the fact that an arbitrary Boolean function to be synthesized might be non-reversible and deal with the resulting problem of ensuring a unique input/output mapping during the actual synthesis process. Experimental evaluations indicate that, following this approach, could provide the basis for an alternative synthesis scheme that allows for synthesizing arbitrary Boolean functions in reasonable time and without the need of a prior embedding process.
引用
收藏
页码:173 / 178
页数:6
相关论文
共 50 条
[21]   Design of Reversible Sequential Circuits Optimizing Quantum Cost, Delay, and Garbage Outputs [J].
Thapliyal, Himanshu ;
Ranganathan, Nagarajan .
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2010, 6 (04)
[22]   A Transformation based Heuristic Synthesis Approach for Reversible Circuits [J].
Roy, Soumya Jyoti ;
Datta, Kamalika ;
Bandyopadhyay, Chandan ;
Rahaman, Hafizur .
2014 INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRICAL ENGINEERING (ICAEE), 2014,
[23]   Synthesis of Reversible Circuits: A View on the State-of-the-Art [J].
Kemtopf, Pawel ;
Perkowski, Marek ;
Podlaski, Krzysztof .
2012 12TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO), 2012,
[24]   Equivalence Checking of Reversible Circuits [J].
Wille, Robert ;
Grosse, Daniel ;
Miller, D. Michael ;
Drechsler, Rolf .
JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING, 2012, 19 (04) :361-378
[25]   Trace Concealment Histogram-Shifting-Based Reversible Data Hiding with Improved Skipping Embedding and High-Precision Edge Predictor (ChinaMFS 2022) [J].
Shi, Hui ;
Hu, Baoyue ;
Geng, Jianing ;
Ren, Yonggong ;
Li, Mingchu .
MATHEMATICS, 2022, 10 (22)
[26]   Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits [J].
Kole, Abhoy ;
Datta, Kamalika ;
Sengupta, Indranil ;
Wille, Robert .
REVERSIBLE COMPUTATION, RC 2015, 2015, 9138 :273-278
[27]   A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits [J].
Noorallahzadeh, Mojtaba ;
Mosleh, Mohammad ;
Ahmadpour, Seyed-Sajad ;
Pal, Jayanta ;
Sen, Bibhash .
INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS, 2023, 36 (05)
[28]   Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits [J].
Wille, Robert ;
Zhang, Hongyan ;
Drechsler, Rolf .
2013 IEEE 43RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2013), 2013, :29-34
[29]   NOVEL REVERSIBLE FAULT TOLERANT ERROR CODING AND DETECTION CIRCUITS [J].
Haghparast, Majid ;
Navi, Keivan .
INTERNATIONAL JOURNAL OF QUANTUM INFORMATION, 2011, 9 (02) :723-738
[30]   Realizing Reversible Circuits Using a New Class of Quantum Gates [J].
Sasanian, Zahra ;
Wille, Robert ;
Miller, D. Michael .
2012 49TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2012, :36-41