Performance enhancement of two-phase quasi-delay-insensitive circuits

被引：1

作者：

Kagotani, K ^{[1
]}

Nanya, T ^{[1
]}

机构：

[1] TOKYO INST TECHNOL,DEPT COMP SCI,TOKYO 152,JAPAN

来源：

SYSTEMS AND COMPUTERS IN JAPAN | 1996年 / 27卷 / 05期

关键词：

quasi-delay-insensitive circuit; autosweeping module; two-phase data-path control;

D O I：

10.1002/scj.4690270504

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

'Two-phase quasi-delay-insensitive circuits control the data-paths by alternating the working-phase and idle-phase. Although the use of Martin's Q-element simplifies the design of such circuits, sequential execution of idle-phases, which consume as much time as working-phases, prevents high-speed circuit operation. The auto-sweeping module (ASM) proposed here allows parallel execution of an idle-phase with the working-phase of the next stage. A few extra circuits are inserted in order to use ASM for every microoperation. A simulation study shows that ASM accelerates the average speed of a multiplier by 58 percent without any increase in the total number of gates.

引用

页码：39 / 46

页数：8

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