Utilizing Circuit Structure for Scan Chain Diagnosis

被引:0
作者
Lo, Wei-Hen [1 ]
Hsieh, Ang-Chih [1 ]
Lan, Chien-Ming [1 ]
Lin, Min-Hsien [1 ]
Hwang, TingTing [1 ]
机构
[1] Natl Tsing Hua Univ, Dept Comp Sci, Hsinchu 300, Taiwan
来源
2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS 2013) | 2013年
关键词
HOLD-TIME; FAULTS;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Scan chain diagnosis has become a critical issue to yield loss in modern technology. In this paper, we present a scan chain partitioning algorithm and a scan chain reordering algorithm to improve scan chain fault diagnosis resolution. In our scan chain partition algorithm, we take into consideration not only logic dependency but also the controllability between scan flip flops. After partition step, the ordering of scan cells is performed to decrease the range of suspect faulty scan cells by a bipartite matching reordering algorithm. The experimental results show that our method can reduce the number of suspect scan cells from 378-31 to at most 3 for most cases of ITC'99 benchmarks.
引用
收藏
页数:6
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