The effect of instruction dependency on superscalar processor performance

Superscalar processors can exploit instruction level parallelism in normal programs. The performance is limited by characteristics of programs and the processor architecture. Because of its complexity, estimating the performance of any superscalar processor design is a difficult task. Quantitative analysis of the effect of instruction dependency on performance is more difficult. To this end, several analytical models of such processors have been proposed. In this paper, a model of super-scaler processors using a network of Multiple Class and Multiple Resource Queues is described and studied. In this model, we are able to model and study instruction classes, instruction dependencies, the cache, the branch unit, the decode unit, the central instruction buffer, the functional units the retirement buffer and the retirement unit in an integrated manner. With analysis, numerical calculation and discrete event simulations, we were able to identify two bottlenecks due to the instruction dependency, predict the performance of a hypothetical superscalar design and quantify the effects of design modifications on performance.