A Low-Power SRAM Using Bit-Line Charge-Recycling Technique

We propose a new low-power SRAM using bit-line Charge Recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtained by recycled charge from its adjacent bit-line capacitance. In order to improve the data retention capability of un-selected cells during write, the power supply lines of memory cells in one column are connected to each other and separated from the power lines of other columns. A test-chip is fabricated in 0.13 mu m CMOS and measurement results show 88% reduction in total power compared to the conventional SRAM (CON-SRAM) at V-DD=1.5V and f-100MHz.