High-performance and low-power challenges for sub-70nm microprocessor circuits (Invited paper)

被引：48

作者：

Krishnamurthy, RK ^{[1
]}

Alvandpour, A ^{[1
]}

De, V ^{[1
]}

Borkar, S ^{[1
]}

机构：

[1] Intel Corp, Intel Lab, Hillsboro, OR 97124 USA

来源：

PROCEEDINGS OF THE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2002年

关键词：

D O I：

10.1109/CICC.2002.1012781

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

CMOS technology scaling is becoming difficult beyond 70nm node, raising new design challenges for high-performance and low-power microprocessors. This paper discusses some of the key paradigm shifts required. Circuit techniques to combat (i) increasing switching and leakage power dissipation, (ii) poor leakage tolerance of large-signal cache arrays and register files, and (iii) worsening global on-chip interconnect scaling trend, are described.

引用

页码：125 / 128

页数：4

共 7 条

[1] Carley L. R., 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477), P109, DOI 10.1109/LPE.1999.799423
[2] Interconnect limits on gigascale integration (GSI) in the 21st century
Davis, JA
Venkatesan, R
Kaloyeros, A
Beylansky, M
Souri, SJ
Banerjee, K
Saraswat, KC
Rahman, A
Reif, R
Meindl, JD
[J]. PROCEEDINGS OF THE IEEE, 2001, 89 (03) : 305 - 324
[3] A 0.5V power-supply scheme for low power LSIs using multi-Vt SOICMOS technology
Fuse, T
Kameyama, A
Ohta, M
Ohuchi, K
[J]. 2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2001, : 219 - 220
[4] Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs
Kanno, Y
Mizuno, H
Tanaka, K
Watanabe, T
[J]. 2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2000, : 202 - 203
[5] A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme
Takahashi, M
Hamada, M
Nishikawa, T
Arakida, H
Fujita, T
Hatori, F
Mita, S
Suzuki, K
Chiba, A
Terazawa, T
Sano, F
Watanabe, Y
Usami, K
Igarashi, M
Ishikawa, T
Kanazawa, M
Kuroda, T
Furuyama, T
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (11) : 1772 - 1780
[6] A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM
Takahashi, M
Nishikawa, T
Hamada, M
Takayanagi, T
Arakida, H
Machida, N
Yamamoto, H
Fujiyoshi, T
Ohashi, Y
Yamagishi, O
Samata, T
Asano, A
Terazawa, T
Ohmori, K
Watanabe, Y
Nakamura, H
Minami, S
Kuroda, T
Furuyama, T
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (11) : 1713 - 1721
[7] TYAGI S, 2000 IEDM, P567

← 1 →