Addressing Thermal and Power Delivery Bottlenecks in 3D Circuits

被引：0
|
作者：
Sapatnekar, Sachin S. [1 ]
机构：
[1] Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA
来源：
PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009 | 2009年
关键词：
PLACEMENT; SIMULATION;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footprint of the chip, as compared to a 2D design. This has ramifications on two critical issues: firstly, it means that more heat is generated per unit footprint, potentially leading to thermal problems, and secondly, more current must be supplied per package pin, leading to possible power delivery bottlenecks. This paper presents an overview of the challenges and solutions in the domain of addressing these two issues in 3D integrated circuits.
引用
收藏
页码：423 / 428
页数：6
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