A Low-Noise Digital-to-Frequency Converter Based on Injection-Locked Ring Oscillator and Rotated Phase Selection for Fractional-N Frequency Synthesis

This paper proposes a low-noise digital-to-frequency converter (DFC) for fractional-N frequency synthesis. The DFC first employs a subharmonic injection-locked ring oscillator (ILRO) to generate low phase noise, high-frequency fixed reference from a crystal oscillator (XO). Delta Sigma modulator (Delta Sigma M) and accumulator are then applied to perform phase randomization and rotation around the multiphase outputs of the ILRO. This modulates the output frequency, while the rotation ensuring the range and linearity of the DFC. Meanwhile, clocking the Delta Sigma M at high frequency greatly suppresses the quantization noise, enabling a wide loop bandwidth for the subsequent phase-locked loop stage. Implemented in UMC CMOS 65-nm technology, the proposed DFC occupies an area of 0.257 mm(2), and is capable of generating frequencies from 390 to 640 MHz with resolution finer than 0.3 kHz. The in-band phase noise is lower than -120 dBc/Hz at 100 kHz, tracking well with the noise performance of the XO. The shaped high-frequency quantization noise only appears beyond 20-MHz frequency offset.