A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits

被引：4

作者：

Hanson, Scott ^{[1
]}

Sylvester, Dennis ^{[1
]}

Blaauw, David ^{[1
]}

机构：

[1] Univ Michigan, Ann Arbor, MI 48109 USA

来源：

ISLPED '06: PROCEEDINGS OF THE 2006 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2006年

关键词：

subthreshold circuits; gate sizing; voltage scaling;

D O I：

10.1109/LPE.2006.4271861

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Mobile applications with battery lifetimes on the order of thousands of days have placed stringent energy requirements on circuits. In this paper, we propose a new energy optimization technique for ultra-low energy circuits operating in the subthreshold regime. Our technique uses simultaneous gate sizing and supply voltage scaling to reduce energy. We demonstrate the effectiveness of our technique on benchmark circuits and offer insight on the roles of the timing distribution and wire capacitance in determining the achievable energy reductions.

引用

页码：338 / 341

页数：4

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