On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit

被引:20
作者
Gu, Jie [1 ]
Eom, Hanyong [2 ]
Kim, Chris H. [2 ]
机构
[1] Texas Instruments Inc, Dallas, TX 75243 USA
[2] Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA
关键词
Decoupling capacitor; microprocessor; on-chip regulator; power supply noise; resonance; switched capacitor; REDUCTION; DESIGN;
D O I
10.1109/JSSC.2009.2020454
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
On-chip resonant supply noise in the mid-frequency range (i.e., 50-300 MHz) has been identified as the dominant supply noise component in modern microprocessors. To overcome the limited efficiency of conventional decoupling capacitors in reducing the resonant supply noise, this paper proposes a low-power digital switched decoupling capacitor circuit. By adaptively switching the connectivity of decaps according to the measured supply noise, the amount of charge provided by the decaps is dramatically boosted leading to an increased damping of the on-chip supply network. Analysis on the charge transfer during the switching events shows a 6-13X boost of effective decap value. Simulations verify the enhanced noise decoupling performance as well as the effective suppression of the first-droop noise. A 0.13 mu m test chip including an on-chip resonance generation circuit and on-chip supply noise sensors was built to demonstrate the proposed switched decap circuit. Measurements confirm an 11X boost in effective decap value and a 9.8 dB suppression in supply noise using the proposed circuit. Compared with previous analog techniques, the proposed digital implementation achieves a 91% reduction in quiescent power consumption with improved tolerance to process-voltage-temperature (PVT) variation and tuning capability for obtaining the optimal switching threshold.
引用
收藏
页码:1765 / 1775
页数:11
相关论文
共 23 条
[1]   A study of soft and hard breakdown - Part II: Principles of area, thickness, and voltage scaling [J].
Alam, MA ;
Weir, BE ;
Silverman, PJ .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (02) :239-246
[2]  
Ang M., 2000, IEEE Intl. Solid-State Circuits Conference ISSCC, P438
[3]   On-chip decoupling capacitor optimization for noise and leakage reduction [J].
Chen, HH ;
Neely, JS ;
Wang, MF ;
Co, G .
16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS, 2003, :251-255
[4]   A 90-nm variable frequency clock system for a power-managed Itanium Architecture processor [J].
Fischer, T ;
Desai, J ;
Doyle, B ;
Naffziger, S ;
Patella, B .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (01) :218-228
[5]   Frequency dependencies of power noise [J].
Garben, B ;
Frech, R ;
Supper, J ;
McAllister, MF .
IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2002, 25 (02) :166-173
[6]  
GU J, 2006, P IEEE INT S LOW POW, P382
[7]  
Gu J., 2006, Symposium on VLSI Circuits, P216
[8]  
Hailu E., 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, P2238, DOI [10.1109/ISSCC.2006.1696285, DOI 10.1109/ISSCC.2006.1696285]
[9]   Design and validation of a power supply noise reduction technique [J].
Ji, G ;
Arabi, TR ;
Taylor, G .
IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2005, 28 (03) :445-448
[10]   Resonance and damping in CMOS circuits with on-chip decoupling capacitance [J].
Larsson, P .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 1998, 45 (08) :849-858