Soft-Well Digital Circuit Design

被引：0

作者：

Abrahamsen, Jens Petter ^{[1
]}

Lande, Tor Sverre ^{[1
]}

机构：

[1] Univ Oslo, Dept Informat, N-0316 Oslo, Norway

来源：

SBCCI2007: 20TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN | 2007年

关键词：

Well biasing; low power design; noise immunity;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we present a novel digital design technique called soft-well circuit design improving digital circuits in fine-pitch technology. Improved noise immunity, higher-speed and reduced static power leakage may be traded for somewhat increased silicon area. The importance of soft-well design may increase in future technology where leakage and noise immunity is expected to severely impact circuit performance.

引用

页码：196 / 201

页数：6

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