共 17 条
- [1] ARM, 2012, ARM CORT A9 TECHN RE
- [2] A power and performance model for network-on-chip architectures [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 1250 - 1255
- [3] da Rosa T.R., 2012, 25th Symposium on Integrated Circuits and Systems Design (SBCCI), P1, DOI DOI 10.1109/SBCCI.2012.6344429
- [4] Eisley N., 2004, P 2004 INT C COMPILE, P104, DOI DOI 10.1145/1023833.1023849
- [7] Exploring NoC-Based MPSoC Design Space with Power Estimation Models [J]. IEEE DESIGN & TEST OF COMPUTERS, 2011, 28 (02): : 16 - 28
- [8] Lungu A., 2009, Proceedings of MEMOCODE'09, P78
- [9] Mishra A.K., P C HIGH PERF COMP N, P1
- [10] Bandwidth-constrained mapping of cores onto NoC architectures [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 896 - 901