FPGAs as accelerators for real-time digital power system simulators

Fully digital power system simulators (DPSS) have been proven on super computers and high end workstations. Real-time DPSSs become necessary when interconnection to field equipment is required. Real-time DPSSs are required to run on relatively inexpensive computers and are overstretching the computation capabilities of modern microprocessors and workstations. Still smaller time steps and thus shorter computation times are required to simulate the detailed higher frequency behavior of some network components. Time step reduction may be achieved by using dedicated pre-processors, co-processors and post-processors. A pre-processor can be thought of as a dedicated highly specialized processor inserted between an input signal and a computer and a post-processor is installed between the computer and an output signal. A co-processor may be regarded as a specialized dedicated math-processor available to the main processor. We have examined the possibility of using dynamically programmable logic devices (FPGAs) as ?-processors in a real-time DPSS. Our objectives were to establish the minimum time step such a post-processor could achieve, identify the fastest transition (highest frequency) a preprocessor could detect and measure the expected speedup a co-processor could provide. We have investigated the difficulties involved with implementing the various ?-processors in field programmable gate arrays (FPGAs) and in connecting them to a TMS320C30 digital signal processor. A set of minimum protocol guidelines was established and a prototype was tested. The portability and evolutivity of the algorithms implemented in the ?-processors was adressed by investigating the possibilities of programming the FPGA algorithms in the C programming language and of using commercially available unmodified hardware. Our conclusions are presented in the paper.