Nanoscale multi-line patterning using sidewall structure

被引:14
作者
Chung, KH
Sung, SK
Kim, DH
Choi, WY
Lee, CA
Lee, JD
Park, BG
机构
[1] Seoul Natl Univ, Inter Univ Semicond Res Ctr, Kwanak Gu, Seoul 151742, South Korea
[2] Seoul Natl Univ, Sch Elect Engn, Kwanak Gu, Seoul 151742, South Korea
来源
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | 2002年 / 41卷 / 6B期
关键词
sidewall patterning technique; etch selectivity; buffer layer; dummy pattern; hard mask; uniformity;
D O I
10.1143/JJAP.41.4410
中图分类号
O59 [应用物理学];
学科分类号
摘要
A patterning technique to define nanoscale multiple lines is developed and optimized using sidewall structure, About 50 nm poly-Si multiple lines, which have 70 nm as one of the narrowest space. are defined by sidewall multi-line patterning technique. These patterns have a good uniformity (deviation 1.5-4.7 nm). In addition, we can control line/space of patterns very easily by sidewall width control in this technique. And this is free from the proximity effect because of the process using sidewall hard mask. So, it is expected that the sidewall multi-line patterning technique can be applied to fabricate single electron devices. quantum devices. and other nanoscale devices.
引用
收藏
页码:4410 / 4414
页数:5
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