A novel VLSI architecture for multidimensional discrete wavelet transform

A novel VLSI architecture for multidimensional discrete wavelet transform (m-D DWT) based on systolic array is proposed. In this method, we divide the input m-D image data into 2(m) independent data streams, and then simultaneously pipeline them into a multi-filter chip, and finally obtain 2(m). samples which are from different DWT subbands per clock cycles (ccs). The proposed architecture performs a decomposition of an N-1 x N-2 x... x N-m image in about N1N2... N-m/(2(m)-1) ccs and requires relatively lower hardware cost than previous architectures. Besides, the advantages of the proposed architecture include very simple hardware complexity, regular data flow and low control complexity.