Ultra-low voltage analog integrated circuits

被引：13
作者：
Chatterjee, Shouri [1 ]
Tsividis, Yannis [1 ]
Kinget, Peter [1 ]
机构：
[1] Columbia Univ, Dept Elect Engn, New York, NY 10027 USA
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 2006年 / E89C卷 / 06期
关键词：
low voltage; 0.5; V; body bias; nano-scale circuits;
D O I：
10.1093/ietele/e89-c.6.673
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The operation of analog circuits from ultra low supply voltages becomes necessary due to semiconductor technology scaling. Yet traditional design techniques cannot be used. In this paper, we review techniques that allow analog circuits to operate with supply voltages as low as 0.5 V. Biasing considerations are given, and robust bias circuits are discussed. For frequency-tunable circuits, a low-voltage MOS varactor tuning technique is presented. The techniques discussed are applied to two different OTA topologies, as well as to an automatically tuned, fifth-order active RC filter. This material is largely based on the work of the authors as described in [1]-[5].
引用
收藏
页码：673 / 680
页数：8
相关论文
共 48 条
[1]  
AHM G, 2005, IEEE INT SOL STAT CI, P166
[2]   A PRECISION VARIABLE-SUPPLY CMOS COMPARATOR [J].
ALLSTOT, DJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (06) :1080-1087
[3]   FULLY DIFFERENTIAL OPERATIONAL-AMPLIFIERS WITH ACCURATE OUTPUT BALANCING [J].
BANU, M ;
KHOURY, JM ;
TSIVIDIS, Y .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (06) :1410-1414
[4]   AN ELLIPTIC CONTINUOUS-TIME CMOS FILTER WITH ON-CHIP AUTOMATIC TUNING [J].
BANU, M ;
TSIVIDIS, Y .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (06) :1114-1121
[5]  
BAZARJANI SS, 1995, IEEE INT SYMP CIRC S, P1021, DOI 10.1109/ISCAS.1995.519940
[6]   Designing 1-V OP amps using standard digital CMOS technology [J].
Blalock, BJ ;
Allen, PE ;
Rincon-Mora, GA .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1998, 45 (07) :769-780
[7]  
BULT K, 2000, P EUR SOL STAT CIRC, P11
[8]   Sub-1-v design techniques for high-linearity multistage/pipelined analog-to-digital converters [J].
Chang, DY ;
Ahn, GC ;
Moon, UK .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2005, 52 (01) :1-12
[9]  
Chatterjee S, 2005, 2005 Symposium on VLSI Circuits, Digest of Technical Papers, P272
[10]   A 0.5-V bulk-input fully differential operational transconductance amplifier [J].
Chatterjee, S ;
Tsividis, Y ;
Kinget, P .
ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2004, :147-150
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