A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm

被引：7

作者：

Hart, Jason M. ^{[1
]}

Cho, Hoyeol ^{[1
]}

Ge, Yuefei ^{[1
]}

Gruber, Gregory ^{[1
]}

Huang, Dawei ^{[1
]}

Hwang, Changku ^{[1
]}

Jian, Daisy ^{[1
]}

Johnson, Tim ^{[1
]}

Konstadinidis, Georgios K. ^{[1
]}

Krishnaswamy, Venkat ^{[1
]}

Kwong, Lance ^{[1
]}

Masleid, Robert P. ^{[1
]}

Mehta, Rakesh ^{[1
]}

Nawathe, Umesh ^{[1
]}

Ramachandran, Aparna ^{[1
]}

Sathianathan, Hari ^{[1
]}

Sheng, Yongning ^{[1
]}

Shin, Jinuk Luke ^{[1
]}

Turullols, Sebastian ^{[1
]}

Qin, Zuxu ^{[1
]}

Yen, King C. ^{[1
]}

机构：

[1] Oracle, Santa Clara, CA 95054 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2014年 / 49卷 / 01期

关键词：

Analog circuit; digital circuit; microprocessor; multi-core; multi-threaded; SPARC; system on chip (SoC); very large scale integration (VLSI);

D O I：

10.1109/JSSC.2013.2284648

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The 3.6 GHz SPARC T5 processor is Oracle's next generation CMT SoC processor implemented in TSMC's 28 nm process with 1.5 billion transistors. Significant performance improvements were made by doubling the previous generations number of cores to 16 and L3 cache size to 8 MB while increasing bandwidth by nearly 3x. Power efficiency was improved through features like DVFS, core-pair cycle skipping and SerDes power scaling. The SPARC T5 processor has been designed to fit in systems that can scale from 1 to 8 sockets, or 128 to 1024 threads, in glueless fashion. The diverse system-level bandwidth requirements of up to 5.65 TB/sec in these systems are met by advanced SERDES design that handles up to 30 dB loss in an area and power efficient manner. The different thermal envelopes of these systems are addressed by power management features that span software, system and chip design.

引用

页码：19 / 31

页数：13

共 7 条

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