Bias voltage controlled memory effect in in-plane quantum-wire transistors with embedded quantum dots

被引：11

作者：

Mueller, C. R. ^{[1
]}

Worschech, L. ^{[1
]}

Schliemann, A. ^{[1
]}

Forchel, A. ^{[1
]}

机构：

[1] Univ Wurzburg, D-97074 Wurzburg, Germany

来源：

IEEE ELECTRON DEVICE LETTERS | 2006年 / 27卷 / 12期

关键词：

floating gate; quantum dot (QD); quantum-wire transistor (QWT); threshold hysteresis;

D O I：

10.1109/LED.2006.886325

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The drain-current through GaAs/AlGaAs quantum-wire transistors (QWTs) with InGaAs quantum dots (QDs) exploited as floating gates is studied for temperatures up to 150 K. It is found that the threshold hysteresis between the up sweep and the down sweep of the gate voltage decreases with increasing bias voltage and is suppressed at a critical bias voltage. It is proposed and demonstrated that these QWTs show logic OR-gate functionality with the option to store the corresponding logic state by switching the bias voltage to zero. The authors explain this behavior by a bias voltage dependent efficiency of the gate to control differently the QDs and the quantum wire.

引用

页码：955 / 958

页数：4