A low-jitter mutual-correlated pulsewidth control loop circuit

被引：22

作者：

Lin, WM ^{[1
]}

Huang, HY ^{[1
]}

机构：

[1] Fu Jen Catholic Univ, Dept Elect Engn, Hsin Chuang 24205, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2004年 / 39卷 / 08期

关键词：

clocks; CMOS integrated circuits; duty cycle; jitter; phase-locked loops; pulsewidth control loop circuit;

D O I：

10.1109/JSSC.2004.831499

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents a low-jitter pulsewidth control loop (PWCL) circuit. A mutual-correlated scheme is implemented to adjust the duty cycle and increase the stability of the PWCL. The design is less sensitive to process variation. The jitter induced by voltage ripple is suppressed. The circuit is implemented using 0.35 mum 1P4M CMOS process. The area of the PWCL is 186 X 143 mum(2). At an operating frequency of 300 MHz, the power dissipation and voltage Apple are reduced by 35.4% and 93.7%, respectively. A test chip is successfully verified to obtain 42-ps jitter at an operating frequency of 960 MHz.

引用

页码：1366 / 1369

页数：4

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