Improved Configuration of Multilevel Inverter with Reduced Semiconductor Devices

In DC/AC power conversion, multi-level inverter (MLI) incorporates a large number of semiconductor devices, which increases its cost and complexity. Moreover, the recently introduced topology uses a large variety of semiconductor switches. Therefore, a great attention is paid toward increasing output voltage levels with less variety and reduced number of switches as compared to conventional topologies. In this paper, improved configuration of symmetrical and asymmetrical MLI is proposed. Improvement is brought on both quantitative and qualitative basis, which led to a reduction in number of semiconductor devices and its variety. Analysis of power losses of the proposed topology is carried out and compared with CHB. A wide range of comparison with recently proposed topologies is made in order to show the novelty and contribution of the proposed topology. Multi-Carrier Pulse Width Modulation strategy is adopted for generating the switching pulses. The detailed simulation study of the proposed topology has been carried out using MATLAB/SIMULINK and validated experimentally for 7-level and 81-level inverter.