Speculative trace scheduling in VLIW processors

被引：0
|
作者：
Agarwal, M [1 ]
Nandy, SK [1 ]
von Eijndhoven, J [1 ]
Balakrishnan, S [1 ]
机构：
[1] Indian Inst Sci, SERC, CADL, Bangalore 560012, Karnataka, India
来源：
ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS | 2002年
关键词：
D O I：
10.1109/ICCD.2002.1106803
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
VLIW processors are statically scheduled processors and their performance depends on the quality of schedules generated by the compiler's scheduler. We propose a new scheduling scheme where the application is first divided into decision trees and then further split into traces. Traces are speculatively scheduled on the processor based on their probability of execution. We have developed a tool "SpliTree" to generate traces automatically. Using dynamic branch prediction for scheduling traces our scheme achieves approximately 1.4x performance improvement over that using decision trees for Spec92 benchmarks simulated on TriMedia(TM).
引用
收藏
页码：408 / 413
页数：6
相关论文
共 50 条
  • [21] Instruction scheduling with k-successor tree for clustered VLIW processors
    Zhang, Xuemeng
    Wu, Hui
    Xue, Jingling
    DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, 2013, 17 (02) : 439 - 458
  • [22] Inter-block scoreboard scheduling in a JIT compiler for VLIW processors
    de Dinechin, Benoit Dupont
    EURO-PAR 2008 PARALLEL PROCESSING, PROCEEDINGS, 2008, 5168 : 370 - 381
  • [23] Scheduling of conditional branches using SSA form for superscalar/VLIW processors
    Choi, SU
    Park, SS
    Park, MS
    1996 INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS, PROCEEDINGS, 1996, : 344 - 351
  • [24] A probability-based instruction combining method for scheduling in VLIW processors
    Iraji, R.
    Sarbazi-Azad, H.
    2006 IEEE INTERNATIONAL CONFERENCE ON COMPUTER SYSTEMS AND APPLICATIONS, VOLS 1-3, 2006, : 672 - +
  • [25] A graph matching based integrated scheduling framework for clustered VLIW processors
    Nagpal, R
    Srikant, YN
    2004 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING WORKSHOPS, PROCEEDINGS, 2004, : 530 - 537
  • [26] Instruction scheduling with k-successor tree for clustered VLIW processors
    Xuemeng Zhang
    Hui Wu
    Jingling Xue
    Design Automation for Embedded Systems, 2013, 17 : 439 - 458
  • [27] Cost-Effective Speculative Scheduling in High Performance Processors
    Perais, Arthur
    Seznec, Andre
    Michaud, Pierre
    Sembrant, Andreas
    Hagersten, Erik
    2015 ACM/IEEE 42ND ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), 2015, : 247 - 259
  • [28] Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage
    Bahtat, Mounir
    Belkouch, Said
    Elleaume, Philippe
    Le Gall, Philippe
    EURASIP JOURNAL ON ADVANCES IN SIGNAL PROCESSING, 2016,
  • [29] Power-aware modulo scheduling for high-performance VLIW processors
    Yun, HS
    Kim, J
    ISLPED'01: PROCEEDINGS OF THE 2001 INTERNATIONAL SYMPOSIUM ON LOWPOWER ELECTRONICS AND DESIGN, 2001, : 40 - 45
  • [30] Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage
    Mounir Bahtat
    Said Belkouch
    Philippe Elleaume
    Philippe Le Gall
    EURASIP Journal on Advances in Signal Processing, 2016
12345