共 50 条
- [2] De-embedding Techniques for Transmission Lines: An Application to Measurements of On-Chip Coplanar Traces 2014 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC), 2014, : 660 - 666
- [5] Characterization and modeling of multiple coupled on-chip interconnects on silicon substrate ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2000, : 333 - 336
- [7] Accurate modeling of lossy silicon substrate for on-chip inductors and transformers design 2004 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2004, : 627 - 630
- [8] The closed environment concept in VLSI on-chip transmission lines design and modeling 10TH IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS, PROCEEDINGS, 2006, : 201 - +
- [9] Equivalent circuit modeling of single and coupled on-chip interconnects on lossy silicon substrate IEEE Top Meet Ekectr Perform Electron Packag, (185-188):
- [10] Substrate loss of on-chip transmission-lines with power/ground wires in lower layer SIGNAL PROPAGATION ON INTERCONNECTS, PROCEEDINGS, 2005, : 201 - 202