Automatic Floorplanning for AI SoCs

被引：7

作者：

Chen, Tai-Chen ^{[1
]}

Lee, Pei-Yu ^{[1
]}

Chen, Tung-Chieh ^{[1
]}

机构：

[1] Maxeda Technol Inc, Hsinchu, Taiwan

来源：

2020 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | 2020年

关键词：

AI; SoC; floorplanning; macro placement; exploration;

D O I：

10.1109/vlsi-dat49148.2020.9196464

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In recent years, artificial intelligence/deep learning field is growing rapidly. The AI system-on-chip designs are actively developed. These designs often have properties of many IP blocks/embedded memories and complicated logic interconnect. In this paper, we propose an automatic floorplanning algorithm by using dataflow information and design exploration techniques to obtain high quality mixed macro and cell placement to handle numerous macros and complicated logic interconnect in AI SoCs.

引用

页数：2

共 7 条

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[2]

Chen ST, 2017, ICCAD-IEEE ACM INT, P496, DOI 10.1109/ICCAD.2017.8203818

[3]

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[5]

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24TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2019), 2019, :557-562

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