共 4 条
- [1] Development of Chip-to-Wafer (C2W) bonding process for High Density I/Os Fan-out Wafer Level Package (FOWLP) PROCEEDINGS OF THE 2016 IEEE 18TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2016, : 435 - 440
- [2] Chip-to-Wafer (C2W) 3D Integration with Well-Controlled Template Alignment and Wafer-Level Bonding 2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2011, : 1 - 6
- [3] Chip-to-Wafer (C2W) flip chip bonding for 2.5D High density interconnection on TSV free interposer 2017 IEEE 19TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2017,
- [4] Development of Bonding Process for High Density Fine Pitch Micro Bump Interconnections with Wafer Level Underfill for 3D Applications PROCEEDINGS OF THE 2013 IEEE 15TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2013), 2013, : 543 - 548