A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector

被引：52

作者：

Chang, Wei-Sung ^{[1
,2
]}

Huang, Po-Chun ^{[1
,2
]}

Lee, Tai-Cheng ^{[1
,2
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 106, Taiwan

[2] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 106, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2014年 / 49卷 / 12期

关键词：

Digital pulse-width modulator (DPWM); divider-less; fractional-N synthesizer; noise folding; phase-locked loop (PLL); SSPLL; ALL-DIGITAL PLL; FREQUENCY-SYNTHESIZER; NOISE; INJECTION; REDUCTION;

D O I：

10.1109/JSSC.2014.2359670

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-noise divider-less PLL, employing a subsampling locked loop, samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation. The frequency synthesizer achieves a low in-band phase noise of 112 dBc/Hz at a 2.3 GHz output frequency. The analysis for the frequency synthesizer, especially for the nonlinear characteristics of the circuits, is proposed. Fabricated in a 0.18 mu m CMOS technology, the frequency synthesizer consumes 9.6 mA and achieves figure-of-merit of -239.1 dB, corresponding to 266 fs rms jitter.

引用

页码：2964 / 2975

页数：12

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