Stack Effect and Logic Restructing on High Fan-in FinFETs Logic Gates

In this paper we discuss the properties of FinFETs with regards to device width quantization, stack effect, logic restructuring, in contrast to the conventional planar MOSFETs. We analyzed stack effect and proposed a device sizing and logic restructuring co-design approach and found that there is no stack effect among FinFETs. We experimented both proposed and conventional logic method using industrial 7nm FinFET and achieved an area reduction by 37.5%, power reduced by 57% for the proposed method when compared to the conventional logic method. But this comes with a delay penalty of 42.2%. Since no stack effect can be observed with FinFETs we have also proposed high Fan-in gates structure and achieved a reduction in input capacitance, which was not considered in planar MOSFETs due to high input capacitance. Also, we proposed a design flow for FinFETs.