74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain

被引:78
作者
Maghari, Nima [1 ]
Kwon, Sunwoo [1 ]
Moon, Un-Ku [1 ]
机构
[1] Oregon State Univ, Sch Elect Engn & Comp Sci, Corvallis, OR 97331 USA
关键词
Analog-to-digital conversion; CMOS analog integrated circuits; delta-sigma modulation; switched-capacitor circuits; ADC; BANDWIDTH;
D O I
10.1109/JSSC.2009.2022302
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a new multi-loop delta-sigma modulator which overcomes the necessity of high DC gain opamps that were needed in previous multi-loop modulators. Enabling the use of low gain opamps also allows low-voltage operation due to the reduced number of transistors between the power supply rails. In addition, all the digital filters are removed from the output of this modulator to minimize the overall system requirement. Instead, an in-loop digital addition facilitates the desired noise transfer functions of both loops. This combines stability advantage of the multi-loop structure with relaxed circuit requirement of the single-loop modulator. A fourth order modulator is implemented in a 0.18 mu m CMOS technology to demonstrate this concept. Measurement results show that, with open-loop opamp gain of less than 35 dB, the implemented prototype IC achieves over 74 dB SNDR at an oversampling ratio of 16. The sampling frequency is 20 MHz and the total power dissipation is 3.2 mW at 1.2 V supply.
引用
收藏
页码:2212 / 2221
页数:10
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