Vertical-Si-Nanowire SONOS Memory for Ultrahigh-Density Application

被引：18

作者：

Chen, Mingcong ^{[1
,2
]}

Yu, Hong Yu ^{[1
,2
]}

Singh, Navab ^{[1
]}

Sun, Yuan ^{[2
]}

Shen, Nan Sheng ^{[1
]}

Yuan, Xiaohong ^{[2
]}

Lo, Guo-Qiang ^{[1
]}

Kwong, Dim-Lee ^{[1
]}

机构：

[1] ASTAR, Inst Microelect, Singapore 117685, Singapore

[2] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore

来源：

IEEE ELECTRON DEVICE LETTERS | 2009年 / 30卷 / 08期

关键词：

Gate all around (GAA); vertical silicon nanowire (SiNW); 3-D Flash memory;

D O I：

10.1109/LED.2009.2024442

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this letter, we present the fabrication and characteristics of a gate-all-around SONOS Flash memory using a vertical Si nanowire (SiNW), which is proposed to be the key building block to realize the 3-D multilevel memory technology for ultrahigh-density application. A highly scaled SiNW with a diameter down to 50 nm using CMOS-compatible technology was achieved. Using an unoptimized SONOS gate stack (with the thickness of SiO2/Si3N4/SiO2 similar to 5/5/6 nm), the devices exhibit well-behaved memory characteristics, in terms of program/erase window, retention, and endurance properties.

引用

页码：879 / 881

页数：3

共 9 条

[1] Future directions and challenges for ETox flash memory scaling [J].

Atwood, G .

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2004, 4 (03) :301-305

[2] Si-nanowire based gate-all-around nonvolatile SONOS memory cell [J].

Fu, J. ;

Singh, N. ;

Buddharaju, K. D. ;

Teo, S. H. G. ;

Shen, C. ;

Jiang, Y. ;

Zhu, C. X. ;

Yu, M. B. ;

Lo, G. Q. ;

Balasubramanian, N. ;

Kwong, D. L. ;

Gnani, E. ;

Baccarani, G. .

IEEE ELECTRON DEVICE LETTERS, 2008, 29 (05) :518-521

[3]

Jung SM, 2006, IEDM Dig. Tech. Papers, P37

[4] Future memory technology: challenges and opportunities [J].

Kim, Kinam .

2008 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PROGRAM, 2008, :5-+

[5]

Lai E.-K., 2006, IEDM Tech. Dig, P41

[6]

Lai S, 2008, INT EL DEVICES MEET, P11

[7]

PARK D, 2004, P SOLID STATE INTEGR, V1, P35

[8]

Tanaka H., 2007, Proc. of IEEE Symp. on VLSI Tech, P14, DOI DOI 10.1109/VLSIT.2007.4339708

[9] Vertical silicon-nanowire formation and gate-all-around MOSFET [J].

Yang, B. ;

Buddharaju, K. D. ;

Teo, S. H. G. ;

Singh, N. ;

Lo, G. Q. ;

Kwong, D. L. .

IEEE ELECTRON DEVICE LETTERS, 2008, 29 (07) :791-794

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