Dynamic noise model and its application to high speed circuit design

被引：4

作者：

Choi, SH ^{[1
]}

Somasekhar, D ^{[1
]}

Roy, K ^{[1
]}

机构：

[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA

来源：

MICROELECTRONICS JOURNAL | 2002年 / 33卷 / 10期

关键词：

noise analysis; modeling; crosstalk; capacitance; simulation;

D O I：

10.1016/S0026-2692(02)00094-0

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A dynamic noise model is developed and applied to analyze the noise immunities of precharge-evaluate circuits. With cross-talk being the main source of noise injection in the circuit, a simple metric represented as voltage-time product can be used to quantify the dynamic noise-margin. This is verified through HSPICE simulation on DOMINO gates. Based on this dynamic noise model, a tool is developed and applied to find the static and dynamic noise-margins at various points in the circuit with the effects of charge share and power/ground bounce taken into account. Obtained noise-margins are translated into maximum allowable coupling capacitances between the nodes for different types of precharge-evaluate logic circuits. The results show the difference in dynamic noise immunities in different logic families. Accurate estimates of dynamic noise-margins and coupling capacitance bounds will help design robust CMOS circuits. (C) 2002 Published by Elsevier Science Ltd.

引用

页码：835 / 846

页数：12

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