A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS

被引：4

作者：

Hoshino, Hiroaki ^{[1
]}

Tachibana, Ryoichi ^{[1
]}

Mitomo, Toshiya ^{[1
]}

Ono, Naoko ^{[1
]}

Yoshihara, Yoshiaki ^{[2
]}

Fujimoto, Ryuichi ^{[2
]}

机构：

[1] Toshiba Co Ltd, Ctr Corp Res & Dev, Kawasaki, Kanagawa 2128582, Japan

[2] Toshiba Co Ltd, Semicond Co, Kawasaki, Kanagawa 2128520, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2009年 / E92C卷 / 06期

关键词：

PLL; synthesizer; VCO; ILFD; phase noise;

D O I：

10.1587/transele.E92.C.785

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80 x 40 mu m(2). The active area of the PLL is 0.31 mm(2).

引用

页码：785 / 791

页数：7

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