An FPGA-based multi-rate interpolator with real-time rate change for a JET test-bench system

Eight independent multi-rate signal interpolators, with real-time change of rate capability, were implemented on a field programmable gate array. The interpolator main building blocks are a cascaded integrator-comb (CIC) filter and the respective compensation filter. The latter performs a fixed rate change of 4 and was implemented as a 129 taps finite impulse response (FIR) filter. The FIR filter coefficients were attained from the MATLAB (R) simulation, based on the inverse sinc(x) function. The CIC was designed to have six stages (N), a differential delay (M) of 1, and a variable rate change factor (R) ranging from 10 up to 10 000. Each interpolator over-samples the multiple data rate digital signals stored at the Joint European Torus (JET) pulse database to a fixed sampling rate of 40 MSPS. These signals are subsequently converted to the analog domain by 16 bit digital-to-analog converters to be used as stimulus for testing real-time control tools and systems at JET.