Corner-parasitics-free low-cost trench isolation

被引:3
作者
Schwalke, U [1 ]
Gabric, Z [1 ]
Elbel, N [1 ]
Bothe, K [1 ]
Hadawi, D [1 ]
Janssen, I [1 ]
Schon, P [1 ]
Inioutis, A [1 ]
Klose, R [1 ]
Plagmann, J [1 ]
机构
[1] Infineon Technol AG, D-81730 Munich, Germany
关键词
extended trench isolation gate technology (EXITGATE); narrow channel effect; self-planarization;
D O I
10.1109/55.798044
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this letter, we present results on a; novel low-cost, corner-parasitics-free trench isolation process. Regarding process complexity, this approach is almost as simple as LOGOS isolation, since the isolation oxide is deposited selectively within the trench. Due to the self-planarizing nature of the fill oxide, the global planarization sequence is largely simplified. With respect to scalability, this approach offers all the advantages of trench isolation with its abrupt transition of active area to isolation. However, in contrast to previous trench isolation schemes, corner-parasitic effects are eliminated by means of the extended trench isolation gate technology (EXTIGATE) device geometry, Asa result, excellent narrow width characteristics and subthreshold curves without kink effect are obtained.
引用
收藏
页码:563 / 565
页数:3
相关论文
共 14 条
[1]  
APPELS JA, 1970, PHILIPS RES REP, V25, P118
[2]   SHALLOW TRENCH ISOLATION FOR ULTRA-LARGE-SCALE INTEGRATED DEVICES [J].
BLUMENSTOCK, K ;
THEISEN, J ;
PAN, P ;
DULAK, J ;
TICKNOR, A ;
SANDWICK, T .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1994, 12 (01) :54-58
[3]   THE CURRENT-CARRYING CORNER INHERENT TO TRENCH ISOLATION [J].
BRYANT, A ;
HAENSCH, W ;
GEISSLER, S ;
MANDELMAN, J ;
POINDEXTER, D ;
STEGER, M .
IEEE ELECTRON DEVICE LETTERS, 1993, 14 (08) :412-414
[4]  
BURENKOV A, 1999, P 29 EUR SOL STAT DE, P684
[5]   A shallow trench isolation using LOCOS edge for preventing corner effects for 0.25/0.18 mu m CMOS technologies and beyond [J].
Chatterjee, A ;
Rogers, D ;
McKee, J ;
Ali, I ;
Nag, S ;
Chen, IC .
IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, 1996, :829-832
[6]  
Davari B., 1988, International Electron Devices Meeting. Technical Digest (IEEE Cat. No.88CH2528-8), P92, DOI 10.1109/IEDM.1988.32759
[7]  
Davarik B., 1989, International Electron Devices Meeting 1989. Technical Digest (Cat. No.89CH2637-7), P61, DOI 10.1109/IEDM.1989.74228
[8]  
ELBEL N, 1998, S VLSI TECHN, P208
[9]  
Fischer E, 1995, VMIC C JUN, P247
[10]  
FUSE G, 1987, IEDM, P732